Fachbereich Informatik - Aktuell

15.02.2017 10:34

Disputation Johannes Kühn

am Freitag, 24. Februar 2017 um 14 Uhr in Raum A104, Sand 1, EG.

FDSOI Design using Automated Standard-Cell-Grained Body Biasing

Berichterstatter 1: Prof. Dr. Wolfgang Rosenstiel
Berichterstatter 2: Prof. Dr. Hideharu Amano

Very large scale Integration of digital circuits has been a key driver of advancements in virtually every field and every aspect of our life. Up until recent years, this advancement has been realized through technology scaling which, however, loses its effectiveness with each scaling step. With the introduction of FDSOI processes at competitive technology nodes, body biasing on an unprecedented scale has been made possible. Body biasing influences one of the central transistor characteristics, the threshold voltage. By being able to heighten or lower the threshold voltage by more than 100mV, the very physics of transistor switching can be manipulated at run time and thereby allows to partially compensate for the fading scaling effect. Furthermore, as body biasing does not lead to different signal levels, it can be applied in a much more fine-grained manner than e.g. Dynamic Voltage Frequency Scaling (DVFS). With the state of the art mainly focused on combinations of body biasing with DVFS, it has thus ignored granularities unfeasible for DVFS. This talk addresses this gap by presenting body bias domain partitioning techniques, and for body bias domain partitionings thereby generated, algorithms that determine body bias assignments. Several different granularities ranging from entire cores to small groups of standard cells were examined using two principal approaches: Designer aided pre-partitioning based determination of body bias domains and a first-time, fully automated, netlist based approach called domain candidate exploration. Both approaches operate along the lines of activation and timing of standard cell groups. These approaches were evaluated using the example of Dynamically Reconfigurable Processors (DRP), a highly efficient class of reconfigurable architectures which consists of an array of processing elements and thus offers many opportunities for generalization towards many-core architectures. Finally, the proposed methods were validated by manufacturing a test-chip. Extensive simulation runs as well as the test-chip evaluation showed the validity of the proposed methods and indicated large improvements in energy efficiency compared to the state of the art. This was accomplished by fine-grained partitioning of the DRP design. This allowed to reduce dynamic power through supply voltage levels yielding higher clock frequencies using forward body biasing, while simultaneously reducing static power consumption in unused parts.